/***
 *** Initialize the ADC and start collecting at 1 kHz immediate evaluation, 
 *** meaning, the ADC ISR is called each sample for evaluation.
 *** NOTE: 1KHz may be 1024 Hz or 1000 Hz depending on which is easier, as we 
 *** don't want to penalize an MCU for requiring much higher speed clocks
 *** to subdivide down to one or the other.
 ***/
void EVSYS_ADC_TC_1kHz(void) 
{     
 /*** 
  *** Configure EVSYS Channel 0 to interconnect ADC and TC
  *** Configure ADC channel 0 Start of conversion 
  *** as user and TC as a trigger generator.
  *** Asynchronous path is required as TC and ADC are not using the same clock generator 
  *** The EVSYS Channel 0 must also have RUNSTDBY and ONDEMAND bits set.
  ***/
 EVSYS->USER[EVSYS_ID_USER_ADC_START].reg = EVSYS_USER_CHANNEL(EVSYS_USER_CHANNEL_0);
 EVSYS->Channel[0].CHANNEL.reg = (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT|
                                  EVSYS_CHANNEL_RUNSTDBY |
                                  EVSYS_CHANNEL_ONDEMAND |        
                                  EVSYS_CHANNEL_PATH_ASYNCHRONOUS|
                                  EVSYS_CHANNEL_EVGEN(EVSYS_ID_GEN_TC0_MC0));      

 /*** Now, Enable ADC result ready interrupt ***/
 ADC->INTENSET.bit.RESRDY = 0x01;

 /*** Enable resready ADC interrupt (ID 22)
  *** At core level
  ***/
 NVIC_EnableIRQ(ADC_RESRDY_IRQn);
 NVIC_SetPriority(ADC_RESRDY_IRQn,1);

 /*** Enable ADC first (Enable Protected, write synchronized) ***/
 ADC->CTRLA.bit.ENABLE    =    0x1;
 while(ADC->SYNCBUSY.reg & ADC_SYNCBUSY_ENABLE);    

 /*** Enable TC then (Enable Protected, write synchronized) ***/
 TC0->COUNT8.CTRLA.bit.ENABLE = 1;
 while(TC0->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_ENABLE);    

}