void configure_Chip_LowPower_features(void)
{

 /*** Enable the cache LOW POWER read mode ***/
 NVMCTRL->CTRLB.bit.READMODE = 1;

 /*** Disable Performance Level forcing the device to be in 
  *** PL0 to reduce power consumption.
  *** User must consider this, if once in active,
  *** the application requires more performances.
  ***/
 PM->PLCFG.bit.PLDIS = 1;

 /*** Enable Dynamic Power Gating enabled ***/
 PM->STDBYCFG.bit.DPGPDSW = PM_STDBYCFG_DPGPDSW_1_Val;

 /*** 4kB SRAM out of 16kB will be retained in STANDBY ***/
 PM->PWCFG.bit.RAMPSWC = PM_PWCFG_RAMPSWC_4KB_Val;

 /*** Buck Regulator mode : Select Buck = 1 ***/
 SUPC->VREG.bit.SEL = 1;
 while(SUPC->STATUS.bit.VREGRDY==0);

 /*** As VREG Switching mode is let in automatic mode 
  *** PM->.STDBYCFG.reg.VREGSMOD=0,
  *** user has to check if the MAINREG low power R
  *** reference is ready. 
  ***/
 while(SUPC->STATUS.bit.ULPVREFRDY==0);

 /*** low power ref for vreg once in Sleep Mode ***/
 SUPC->VREG.bit.VREFSEL = 1;

 /*** Set Low power Mode Efficiency 
  *** for the Low Power Voltage Regulator (LPVREG)
  *** !!!! Apply this when power voltage is above 2.5 V !!!! 
  ***/
 SUPC->VREG.bit.LPEFF = 0x1;

}